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Technology R & D

Technology R & D

 R & D Team 


2016-2017 R&D project: increase the aspect ratio to 30:1 or higher; large and thin backplane capability; impedance control tolerance reduced to ±5% or less; introduction of advanced electroplating and light forming methods;

Advanced tool system to improve the alignment between layers; continue to verify new materials for HDI, high speed, low loss, thinner structure and component applications (such as ZETA®, I-Tera®, I-speed®, Tachyon G100®, Megtron7N, andEMC 891k&890); deep microvia research (L1-L3, thickness-to-diameter ratio 1:1 or greater); heat dissipation solution: metal core board, conductive paste (Ormet and Tatsuta);

Buried components PCB board
 
 

 

 R&D Investment 


2016-2017 R&D project: increase the aspect ratio to 30:1 or higher; large and thin backplane capability; impedance control tolerance reduced to ±5% or less; introduction of advanced electroplating and light forming methods;

Advanced tool system to improve the alignment between layers; continue to verify new materials for HDI, high speed, low loss, thinner structure and component applications (such as ZETA®, I-Tera®, I-speed®, Tachyon G100®, Megtron7N, andEMC 891k&890); deep microvia research (L1-L3, thickness-to-diameter ratio 1:1 or greater); heat dissipation solution: metal core board, conductive paste (Ormet and Tatsuta);

Buried components PCB board
 

 Research Project 


2016-2017 R&D project: increase the aspect ratio to 30:1 or higher; large and thin backplane capability; impedance control tolerance reduced to ±5% or less; introduction of advanced electroplating and light forming methods;

Advanced tool system to improve the alignment between layers; continue to verify new materials for HDI, high speed, low loss, thinner structure and component applications (such as ZETA®, I-Tera®, I-speed®, Tachyon G100®, Megtron7N, andEMC 891k&890); deep microvia research (L1-L3, thickness-to-diameter ratio 1:1 or greater); heat dissipation solution: metal core board, conductive paste (Ormet and Tatsuta);

Buried components PCB board
 
Deep microporous technology

Deep microporous technology

Provides higher wiring density, optimized impedance control, RF microvia solution, solid copper plating on the surface of BGAs, and improved current carrying capacity

Metal core PCBs

Metal core PCBs

Thermal management solution, excellent heat distribution, enhanced thermal conductivity, copper core CTE 17ppm/C, thermal conductivity 385 WmK

Buried resistance

Buried resistance

Embedded resistance, aerospace, communications, microwave and medical
 

  
Internal interconnection of each layer

Internal interconnection of each layer

Fully internal laminated holes increase the freedom of circuit design, solid copper provides better reliability and better electrical performance
 

Buried component PCB

Buried component PCB

Embedded resistance and printed internal resistance, embedded capacitance/dielectric layer insulation, flattened converters and transformers, embedded semiconductors and thin wafers, embedded components on rigid-flex board

Eliminate height restrictions

Eliminate height restrictions

Embedded chip for Gold Wire Bonding, connectors with limited thickness

 

 
 

 Technical Route 


2016-2017 R&D project: increase the aspect ratio to 30:1 or higher; large and thin backplane capability; impedance control tolerance reduced to ±5% or less; introduction of advanced electroplating and light forming methods;

Advanced tool system to improve the alignment between layers; continue to verify new materials for HDI, high-speed, low-loss, thinner structure and component applications (such as ZETA®, I-Tera®, I-speed®, Tachyon G100®, Megtron7N, andEMC 891k&890); deep microvia research (L1-L3, thickness-to-diameter ratio 1:1 or greater); heat dissipation scheme: metal core board, conductive paste (Ormet and Tatsuta) embedded components PCB board
 
Technology Roadmap
  inch [mm] Standard
2018
Batch
2018
Sample
2018-2019
R&D
2020
Key attributes Number of layers Up to 16L 18L to 32L 32L to 40L >40+L
Min/max thickness 012" [.30]/.125" [3.2] .008" [.20]/.200" [5.08] .006" [.15]/.250" [6.35] TBD/≥.300" [7.62]
Maximum pnl size 18x24[457x610] 24x30 [610 x 762] 24x42 [610 x 1067] To be determined
 
Minimum line width and line spacing (copper thickness) Inner layer .004" [.10] 1 .003" [.076] H .002" [.05] 5um <.002" [.05] Qoz
Outer layer .004" [.10] T .003" [.076] Q .002" [.05] 5um <.002" [.05] Qoz
tolerance ±.0005" [.013] ±.0003" [.008] ±.00025" [.006] ±.0002" [.005]
 
Mechanical hole size Drill bits .008" [.20] .006" [.15] .006" [.15] .006" [.15]
Hole pad diameter +.008" [.20] +.008" [.20] +.006" [.15] .006" [.15]
Aspect ratio 10:1 20:1 25:1 30:01:00
Base copper weights: 1=1oz H=1/2 OZ, T=3/8 OZ, Q=1/4 OZ
Pore ​​structure Laser hole layer 1+N+1 2+N+2 3+N+3 ELIC
Buried hole Yes Yes Yes Yes
Stacked holes Stacked on Sub Yes Yes Yes
 
Laser hole Smallest hole .004" [.10] .004" [.01] .003" [.76] .002" [.05]
Hole pad diameter +.008" [.20] +.006" [.15] +.004" [.10] +.003" [.076]
Aspect ratio 0.8:1 1:1 1:1 1:1
 
Conduction & non-conduction hole filling Minimum aperture .008" [.20] .008" [.20] .006" [.15] <.006" [.15]
Aspect ratio 12:1 18:1 26:1 30:1
 
Solder mask Counterpoint ±.002" [.05] ±.0015" [.038] ±.001" [.025] Tangency
Minimum window .004" [.10] .003" [.076] .002" [.05] SMDP
The smallest green oil bridge .003" [.08] .002" [.05] .0015" [.038] Eng Eval
Surface treatment ENIG, OSP ENEPIG Thick Gold Multiple Finishes To be determined
Im Sn, Im Ag Wire Bondable Gold
LF HASL Multiple Finishes
Hard Gold Body
Material selection Rogers 3000/4000 Ultra Low Loss Dk/Df   Burying
the buried element
Halogen Free FR4 EMC 828, EMC 888K I-Tera® I-Speed® EMC 891K Tachyon 100G® MetroWave
Buried Capacitance Polyimid, Megtron 6N Megtron 7N, EMC 890K
408 HR Nelco-13s Hybrid PCBs Thermal Management PCBs